Hardware Designs for LT Coding

Faculty of Electrical Engineering, Mathematics and Computer Science CAS-MS-2006-02 The concept of Network-on-Chip (NoC) is becoming a main trend in the area of System-on-Chip (SoC) design. In NoC communications the transmission data may have errors raised by noises or technologies. Forward-Error-Correction (FEC) schemes can be used to improve the systems’ reliability by detecting and correcting errors on the receivers. Many FEC algorithms were investigated during the past few decades, but the realization of these FEC algorithms in hardware is still an exciting research area. Hardware based implementations can be several orders of magnitudes faster than software based methods so it is interesting to see what kind of FEC scheme can be implemented on hardware environment and how well it works. In our project, we study the LT Codes which comes from the new coding family of the Digital Fountain Codes. In this algorithm, a sparse random parity-check graph is dynamically generated on both encoder and decoder to recover the transmitted messages. The LT Codes are also known as the first realization of rateless codes, in the sense that it can generate potentially limitless codeword symbols from original data and self-adjust to channels with different BitErasure-Rate. LT Codes also have a very low encoding/decoding cost when comparing with some traditional block codes, e.g. Reed Solomon(RS) codes and Low-DensityParity-Check(LDPC) codes. Therefore, LT Codes are very suitable for multi-channel data transmitting environments such as NoC network architecture. In this thesis, two BEC models are proposed on different OSI layers and used to analyze the performance of LT Codes, we describe an efficient hardware architecture of LT Coder which has a nearly linear time complexity, we presents the analysis results of LT Codes in terms of time, area and coding performance. Hardware Designs for LT Coding